1. Field of the Invention
The present invention relates to the area of asynchronous circuits, and more particularly, to a self-timed data pipeline apparatus and design methodology.
2. Related Application
This application is related to copending U.S. patent application Ser. No. 07/892,535, filed Jun. 1, 1992, entitled, "Self-Timed Mesh Routing Chip With Data Broadcasting."
3. Art Background
In recent years, there has been an increased interest in asynchronous circuits within the data processing arts. This increased interest is attributable to the fact that asynchronous, or self-timed circuits are able to operate at particularly fast speeds, much faster, for example, than equivalent clocked circuits. Of particular interest are data pipelines which do not operate in accordance with a globally distributed clock, but are instead, self-timed, and therefore, particularly fast. Self-timed data pipelines can be configured to perform a variety of functions including, for example, multiplication, addition, multiplexing, demultiplexing, parity checking, or message routing.
Prior art data pipelines were typically incorporated within larger, highly customized parts. These highly customized parts often used specialized elements or specialized designs at the transistor-level to construct the desired self-timed data pipeline. It will be appreciated that such an approach to designing a self-timed data pipeline suffers from a number of shortcomings. Designing and producing a data pipeline in a customized part can be a time-consuming process. It can also be costly to fabricate and test such a part. In addition, the final product of such an approach is a very application-specific, customized part which does not readily lend itself to replication or adaptation to other contexts.
As will be described, the present invention departs from the prior art approach of designing a self-timed data pipeline in a customized part using specialized elements and transistor-level designs. Instead, the present invention provides for a self-timed pipeline comprising a plurality of pipeline stages, with each pipeline stage comprised of data flip-flops and combinational logic utilizing common logic elements available in commodity application specific integrated circuits. The present invention, accordingly, provides for an inexpensive and versatile data pipeline apparatus and design methodology.